100315F

100315 NSC

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n Low output to output skew (≤50 ps) n Differential inputs and outputs n Secondary clock available for system level testing n 2000V ESD protection n Voltage compensated operating range: −4.2V to −5.7V n Standard Microcircuit Drawing (SMD) 5962-9469601 Logic Diagram Connection Diagram Pin Names Description CLKIN, CLKIN Differential Clock Inputs CLK 1–4, CLK1–4 Differential Clock Outputs TCLK Test Clock Input (Note 1) CLKSEL Clock Input Select (Note 1) Note 1:TCLK and CLKSEL are single-ended inputs, with internal 50 kΩ pull- down resistors. Truth Table CLKSEL CLKIN CLKIN TCLK CLK N CLK N LL H X L H LH L X H L HX X L L H HX X H H L L = Low Voltage Level H = High Voltage Level X = Don’t Care DS100319-1 Flatpak DS100319-2 August 1998

100315 Low-Skew Quad Clock Driver

© 1998 National Semiconductor Corporation DS100319 www.national.com

Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired Storage Temperature −65˚C to +150˚C Maximum Junction Temperature (T Ceramic +175˚C Case Temperature under Bias (TC ) –55˚C to +125˚C VEE Pin Potential to Ground Pin −7.0V to +0.5V Input Voltage (DC) V CC to +0.5V Output Current (DC Output HIGH) −50 mA Operating Range (Note 2) −5.7V to −4.2V ESD (Note 3) ≥2000V Recommended Operating Conditions Case Temperature (TC ) Military −55˚C to +125˚C Supply Voltage (VEE ) −5.7V to −4.2V Note 2:Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3:ESD testing conforms to MIL-STD-883, Method 3015. Military Version VEE = −4.2V to −5.7V, VCC = VCCA = GND (Note 6) Symbol Parameter Min Typ Max Units T C Conditions Notes VOH Output HIGH −1025 −870 mV 0˚C to VIN = VIH(Max) or VIL(Min) Loading with 50Ω to −2.0V (Notes 4, 5, 6) Voltage +125˚C −1085 −870 mV −55˚C VOL Output LOW −1830 −1620 mV 0˚C to Voltage +125˚C −1830 −1555 mV −55˚C V OHC Output HIGH −1035 mV 0˚C to VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2.0V Voltage +125˚C −1085 mV −55˚C (Notes 4, 5, 6) VOLC Output LOW −1610 mV 0˚C to Voltage +125˚C −1555 mV −55˚C VEE = −4.2V to −5.7V, VCC = VCCA = GND (Note 6) Symbol Parameter Min Typ Max Units T C Conditions Notes VDIFF Input Voltage 150 mV −55˚C to Required for Full (Notes 4, 5, 6)Differential +125˚C Output Swing VCM Common Mode V CC − 2.0 V CC − 0.5 V −55˚C to (Notes 4, 5, 6)Voltage +125˚C VIH Single-Ended −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 4, 5, 6, 7)Input High Voltage +125˚C for All Inputs VIL Single-Ended −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 4, 5, 6, 7)Input Low Voltage +125˚C for All Inputs IIH Input HIGH Current 150 µA −55˚C to V IN = VIH(Max) (Notes 4, 5, 6)CLKIN, CLKIN +125˚C TCLK 450 µA CLKSEL 380 µA I CBO Input Leakage −10 µA −55˚C to V IN = VEE (Notes 4, 5, 6)Current +125˚C IEE Power Supply −80 −25 mA −55˚C to (Notes 4, 5, 6)Current, Normal +125˚C Note 4:F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. www.national.com 2

Note 5:Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6:Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7:Guaranteed by applying specified input condition and testing VOH /VOL . after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 9:Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 10:Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 11:Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data). Note 12:Maximum output skew for any one device. Note 13:Shown for testing CLKIN to CLK1 in the differential mode. Note 14:L1, L2, L3 and L4= equal length 50Ω impedance lines. Note 15:All unused inputs and outputs are loaded with 50Ω in parallel with≤3 pF to GND. Note 16:Scope should have 50Ω input terminator internally. FIGURE 1. AC Test Circuit

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16 Lead Ceramic Flatpak (F)

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