100314D

100314 NSC

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n 35% power reduction of the 100114 n 2000V ESD protection n Pin/function compatible with 100114 n Voltage compensated operating range= −4.2V to −5.7V n Standard Microcircuit Drawing (SMD) 5962-9162901 Logic Symbol Pin Names Description D a–D e Data Inputs D a–D e Inverting Data Inputs O a–O e Data Outputs O a–O e Complementary Data Outputs DS100299-1 August 1998

100314 Low Power Quint Differential Line Receiver

© 1998 National Semiconductor Corporation DS100299 www.national.com

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Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired (Note 1) Storage Temperature (T STG ) −65˚C to +150˚C Maximum Junction Temperture (TJ) Ceramic +175˚C Pin Potential to Ground Pin (VEE ) −7.0V to +0.5V Input Voltage (DC) V EE to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V Recommended Operating Conditions Case Temperature (TC ) Military −55˚C to +125˚C Supply Voltage (VEE ) −5.7V to −4.2V Note 1:Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2:ESD testing conforms to MIL-STD-883, Method 3015. Military Version VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C (Note 5) Symbol Parameter Min Typ Max Units T C Conditions Notes VOH Output HIGH Voltage −1025 −870 mV 0˚C to V IN = VIH (Max) or VIL (Min) Loading with 50Ω to −2.0V +125˚C −1085 −870 mV −55˚C (Notes 3, 4, 5) VOL Output LOW Voltage −1830 −1620 mV 0˚C to +125˚C −1830 −1555 mV −55˚C VOHC Output HIGH −1035 mV 0˚C to V IN = VIH (Max) or VIL (Min) Loading with 50Ω to −2.0VVoltage +125˚C −1085 mV −55˚C (Notes 3, 4, 5) VOLC Output LOW −1610 mV 0˚C to Voltage +125˚C −1555 mV −55˚C V BB Output Reference −1260 mV 0˚C to I VBB = 0 µA, VEE = 4.2V (Notes 3, 4, 5) Voltage +125˚C −1380 −1260 mV 0˚C to I VBB = −250 µA, VEE = −5.7V +125˚C (Notes 3, 4, 5) −1396 mV −55˚C I VBB = −350 µA, VEE = −5.7V VDIFF Input Voltage 150 mV −55˚C to Required for Full Output Swing (Notes 3, 4, 5) Differential +125˚C V CM Common Mode V CC − 2.0 V CC − 0.5 V −55˚C to (Notes 3, 4, 5) Voltage +125˚C VIH Single-Ended −1165 −870 mV −55˚C to Guaranteed HIGH Signal for All (Notes 3, 4, 5, 6) Input High Voltage +125˚C Inputs (with D n tied to VBB ) VIL Single-Ended −1830 −1475 mV −55˚C to Guaranteed LOW Signal for All (Notes 3, 4, 5, 6) Input Low Voltage +125˚C Inputs (with D n tied to VBB ) IIH Input HIGH Current 50 µA 0˚C to V IN = VIH (Max),D a–D e = VBB , +125˚C D a–D e = VIL (Min) (Notes 3, 4, 5) 70 µA −55˚C ICBO Input Leakage −10 µA −55˚C to V IN = VEE ,D a–D e = VBB , (Notes 3, 4, 5) Current +125˚C D a–D e = VIL (Min) IEE Power Supply −65 −25 mA −55˚C to D a–D e = VBB , (Notes 3, 4, 5) Current +125˚C D a–D e = VIL (Min) Note 3:F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 4:Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 5:Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 6:Guaranteed by applying specified input condition and testing VOH /VOL . www.national.com3

after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8:Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 9:Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 10:Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data). FIGURE 1. AC Test Circuit

FIGURE 2. Propagation Delay and Transition Times

Physical Dimensionsinches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) 24-Lead Quad Cerpak (F) www.national.com7

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.