100130 NSC
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 6
Technical content
NATIONAL SEMICOND (LOGIC) b1E D M™ 6501122 0075928 753 MMNSCL National Not Intended For New Designs | = Semiconductor EU-07-08 OS 5 100130 “Ee Triple D Latch 4 iad General Description re. The 100130 contains three D-type latches with true and (or both) are HIGH, a latch stores thellast valid data present complement outputs and with Common Enable (Ec), Master _ on its Dp input before E,, or Ec goes! ‘HIGH. Set (MS) and Master Reset (MR) inputs. Each latch has its goth Master Reset (MR) and Master Set (MS) inputs over- own Enable (E,), Direct Set (SD,) and Direct Clear (CDp) ride the Enable:itiputs. The individual CD, and ‘SDp also inputs. The Q output follows its Data (D) input when both En override the Enable inputs. All inputs have 50 k?. pull-down and Ec are LOW (transparent mode). When either En or Ec resistors, eee . tty? Ordering Code: see sections Ie Logic Symbol . (J J (J . CDp-CD2 Individual Direct Clear Inputs 28 Ss. | sd-sd2 Individual Direct Set inputs fo EE Do Oy Oy ? =} Eo-Ea Individual Enable Inputs (Active LOW) Ec Common Enable Input (Active LOW) joo : 4 Do-Da Data Inputs Joos ‘he eugl| MR Master Reset input ee a nS Master Set Input hang y Qo-Q2 Data Outputs ha aut Go-Be Complementary Data Outputs De we fe mrs oO mf apt, w aumase-e Connection Diagranis “ft 2dePin DIP’ 24-Pin Quad Cerpak sh Dy SD; MR Vee Ep MS 0,41 ” 24b-sp, won, Be 23-00, 7 24 23 22 21 20 19 aes abe, gs 18+ spy ope 2-0, oo, 42 170, i Gas 20f-so, S0g—73 16 Em on 18}-ur Co,—t4 150 Vea 7 18}-Ver Bs Dm
48 Whe, 0,45 13 a
ade 16}-us 7 8 9 10 11 12 G10 15F=SDp Q , VocVocad 2 ait taboo, TF /0082-2 Oy 412 13 Ey TUF /se52-1 3-13
ONAL SEMICOND (LOGIC) bIE D M™ b50)122 0075929 bIT BNSC] Ss Logic Diagram . ™ SDp° Oo Cp SO, Dy ©D; Sbz Oz ExEc C4 i» So Co So Co| Cae pl Lt | TT wa —DS a es CD % a init te TUF 0082-5 Truth Tables (cach Later) SUE Latch Operation Asynchronous Operation ° Ring MR lsjefe(efal« | [ejele[slal = | cfede L L bye’? x | x | x H L H H L L L L BE x x x L H L x H x L L Uleheas | S| X x x H H u x x H L L Latehed* ¥ “Retans data presented betore E positive vansiion ae H = HIGH Voltage Lovet ht Le L = LOW Voltage Level ner X = Don't Care U = Undetned Pe 344
NATIONAL SEMICOND (LOGIC) bLE D m@™ b501222 0075930 301 MMNSCL . 3 Absolute Maximum Ratings 3 Above which the useful life may be impaired. (Note 1) s it Military/Aerospace specitied devices are required, Case Temperature under Bias To OC to +85°C Please contact the National Semiconductor Sales Vee Pin Potential to Gr = " EE ial to Ground Pin 7.0V to +0.5V. Oftice/Distributors tor availability and specitications, Input Voltage (DC) Vee to +0.5V wee smperatie BBC to + 160°C Output Current (DC Output HIGH) —50 mA laximum Junction Temperature (T) +150°C Operating Range (Note 2) =57Vt0 -4.2V Ver = ~4.5V, Voc ~ Voca = GND, To = 0°C to +85°C (Note 3) Symbol | Parameter [win [typ | Max | Unite Conditions (Note 4) You | Ouputichvotage [1035 | 955 |" =a80 |) | Var=Viwonen | Loading win Vin Input HIGH Voltage _ _ Guaranteed HIGH Signal 1165 880 mv for All Inputs Vin Input LOW Voltage _ Guaranteed LOW Signal 1475 mv for All Inputs Vez = —4.2V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbot [Parameter [win | Tye_[ max | unio | Gondtons wows Vin Input HIGH Voltage ~870 mv Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage _ Guaranteed LOW Signal 1475 mv for All Inputs in Input Low Curent [oso [TT nA] Viv = Vuruum Ver = ~4.8V, Voc = Voca = GND, To = 0°C to +85°C (Note 3) Symbot [Parameter [win [typ [wax [vats | Gonations mote Vou Output HIGH Vortage [i095 [| 880 | my | YiN=Vin(ay | Loading with WY Vouc QuipurricHvortage | “1045 | [|TV = Varga | Loading with Via Input HIGH Voltage _ _ Guaranteed HIGH Signal 1165 880 mv for All Inputs Vie Input LOW Voltage 1490 mv Guaranteed LOW Signal 3 for All Inputs | tmputow current [080 [a n= Vice Note ts Absolute maximum ratngs ar those values beyond which the dewce may be damaged o: havo ts ust le mpaved Functional operanon unger paws ‘condone not ped Note 2: Parametre valves spocited at —4.2V to — av Note 3: Te spected tots represent th “worst casa” value forthe parameter. Since those "worst ca8e values normaly occur atthe temperaure extremes, ‘ssbonel nase mmunty and guard baring canbe achoved by decreasng to alowable system oporung ros Note 4: Conditions for tastng shown mth tables ave chosen to guarantee operabon under “worst case" condioons 3415
NATIONAL SEMICOND (LOGIC) 61E D MM 6502122 0075931 248 MENSCH) S| Vee = —42V to —4.8V unless otherwise specified, Voo = Voca = GND, To = OC to + 85°C tie ha Input HIGH Current ‘baad ger Dn 350 See oe Dp, SDp 530 pA Vink = MA ten) En 240 aot * Eo, MR, MS. 450 x Ceramic Dual-in-Line Package AC Electrical Characteristics **" Vee = —4.2V to —4.8V, Voc = Voca = GND i symbol [re EE | Conditions oso 61.60 | 050 1.70 | 2 ¥90 teHL Output (Transparent Mode) bei wit Figures 1 and 2 tPLH Propagation Delay hid s fieeee [ow ee [oe [om eo | =| tein | Propagation Delay Ga. iy ; tee CDq, SOp, En to Output 050 200 | BBs. 1.75 Jrp.eo 2.00 Figures 1, 2and 9 tPLH Propagation Delay ee ; ton MS, MR to t [1020 | 110 BMF] 1.10 2.60 Figures 1 and 2 Ty tru Transition Time eee isa thn, 20% to 80%, 80% 10.20% | o4% gre ed 1.60 | 045 1.60 Figures 1 and 2 ts Setup Time Gh, a } Do-D2 090 “nts | 0. 0.90 CD $Dp (Release Time) | 1.20 ss fRteto 1.40 Figures 3 and 4 MR, MS (Release Time) 1.90 1.90 2.00 | HasTineDe-02 ube «| oo | woe | iow twit) | Pulsewidth LOW 4) | age a ; En Ec bar a Figure 2 tpw(H) Pulse Width HIGH . ) f Dp, SDp, MR, MS ae 2.00 Figures As Bee Pre, l 3-16
FIGURE 2. Enable Timing